Deep Packet Inspection

Content Inspection

ECLA developed the first commercially available Content Inspection (CI) chip and licensed it to Raqia Networks in 2001.

The Raqia device, the ReGXP2G, has a look-aside architecture, operates at 2.4Gbps. and has a glue-less interface to NPUs.

The ReGXP2G product brief is here.

Please contact us at on how to obtain devices, the complete data sheet or more information.


ECLA's CI-DPI Processor is optimized to operate at up to 40Gbps, is fully customizable and is available for either a Xilinx Virtex 6 device or an Altera Stratix4 device.


  • Complete Deep Packet Inspection in an FPGA core.
  • Deterministic performance.
  • Full duplex operations up to 40Gbps.
  • Inspects every byte of the packet, header as well payload, as well across packet boundaries.
  • Optional on-chip database storage.
  • Complete header checking, including checksum checking.
  • Implements an EDFA (Efficient Finite Automata) based architecture. Each EFA combines a DFA Engine, a Hashing Engine and an optimizer for most efficient operation and database storage.
  • Header check settings using dedicated registers or through regular expressions.
  • Payload checking using regular expression signatures using our regular expression compiler.
  • Supports a very large number of rules with DDR2, or DDR3 or RLDRAMII.
  • Supports incremental rules update.
  • Common API across all CI Processor family.
  • Support for hundred of thousands signatures.
  • Support for PERL compatible regular expressions.
  • Availability of a rule compiler with incremental rule update support.
  • Availability of a software simulator and a software emulator.
  • Easy system integration.
  • Customizable front end interface (PCI-Express, QDR, Ethernet or custom interface).
  • Scalable performance.
  • Look-aside operation with a customizable interface.
  • Look-aside operation with a PCI-Express interface.
  • In-line (bump in the wire) operation with a Ethernet or a SPI-4 Interface.